und der zweite Teil:
--- Devices/AirLinked/board.h.CSM Fri Feb 01 11:07:16 2013
+++ Devices/AirLinked/board.h.CSM Sun Jun 08 19:57:59 2014
@@ -60,10 +60,14 @@
#define HAS_FASTRF // PROGMEM: 468b RAM: 1b
#define HAS_RF_ROUTER
#define HAS_ASKSIN
+//#define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#define HAS_ESA
#define HAS_INTERTECHNO
#define BOARD_ID_STR "CSM868"
+//#define CUL_HW_REVISION "CSM"
#define TTY_BUFSIZE 132
--- Devices/AirLinked/board.h.HM-LC-Sw1-PI Fri Feb 01 11:07:16 2013
+++ Devices/AirLinked/board.h.HM-LC-Sw1-PI Sun Jun 08 19:58:07 2014
@@ -73,10 +73,14 @@
#define HAS_FASTRF // PROGMEM: 468b RAM: 1b
#define HAS_RF_ROUTER
#define HAS_ASKSIN
+//#define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#define HAS_ESA
#define HAS_INTERTECHNO
#define BOARD_ID_STR "CSM868"
+//#define CUL_HW_REVISION "HM-LC-Sw1-PI"
#define TTY_BUFSIZE 132
--- Devices/AirLinked/board.h.RWE_PSS Fri Feb 01 11:07:16 2013
+++ Devices/AirLinked/board.h.RWE_PSS Sun Jun 08 19:57:11 2014
@@ -55,10 +55,14 @@
#define HAS_FASTRF // PROGMEM: 468b RAM: 1b
#define HAS_RF_ROUTER
#define HAS_ASKSIN
+//#define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#define HAS_ESA
#define HAS_INTERTECHNO
#define BOARD_ID_STR "CSM868"
+//#define CUL_HW_REVISION "RWE_PSS"
#define TTY_BUFSIZE 132
--- Devices/AirLinked/board.h.zCSM Mon Jul 01 12:05:26 2013
+++ Devices/AirLinked/board.h.zCSM Sun Jun 08 19:56:30 2014
@@ -66,10 +66,14 @@
#define HAS_FASTRF // PROGMEM: 468b RAM: 1b
#define HAS_RF_ROUTER
#define HAS_ASKSIN
+//#define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#define HAS_ESA
#define HAS_INTERTECHNO
#define BOARD_ID_STR "CSM868"
+//#define CUL_HW_REVISION "zCSM"
#define TTY_BUFSIZE 132
--- Devices/AirLinked/culfw.c Fri Jul 05 13:03:32 2013
+++ Devices/AirLinked/culfw.c Sun Jun 08 19:54:29 2014
@@ -36,7 +36,7 @@
#include "intertechno.h"
#endif
-#ifdef HAS_ASKSIN
+#if defined(HAS_ASKSIN) || defined(HAS_ASKSIN_PLL_HELPER) || defined(HAS_MS_TIMER0) || defined(HAS_MS_TIMER3)
#include "rf_asksin.h"
#endif
@@ -134,12 +134,16 @@
// }
// Setup the timers. Are needed for watchdog-reset
-#if defined (HAS_IRRX) || defined (HAS_IRTX)
+#ifdef HAS_IRRX
ir_init();
// IR uses highspeed TIMER0 for sampling
OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
#else
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
+#else
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
@@ -148,6 +152,16 @@
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+#ifdef HAS_MS_TIMER3
+ uint8_t sreg = SREG;
+ cli();
+ OCR3A = 999; // 999 -> Timer3: 1ms = 8MHz/8/1000 interrupt clock
+ SREG = sreg;
+ TCCR3A = 0;
+ TCCR3B = _BV(CS31) | _BV(WGM32); // Timer3: 1us = 8MHz/8 base clock
+ TIMSK3 = _BV(OCIE3A);
+#endif
+
clock_prescale_set(clock_div_1);
MCUSR &= ~(1 << WDRF); // Enable the watchdog
@@ -202,6 +216,9 @@
#endif
#if defined (HAS_IRRX) || defined (HAS_IRTX)
ir_task();
+#endif
+#ifdef HAS_ASKSIN_PLL_HELPER
+ rf_asksin_check_PLL_task();
#endif
}
--- Devices/CCD/board.h Mon Mar 17 14:45:54 2014
+++ Devices/CCD/board.h Sun Jun 08 20:00:47 2014
@@ -51,6 +51,9 @@
#define HAS_RAWSEND //
#define HAS_FASTRF // PROGMEM: 468b RAM: 1b
#define HAS_ASKSIN
+//#define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#define HAS_MORITZ
#define HAS_ESA
#define HAS_TX3
@@ -64,6 +67,9 @@
#define BUSWARE_CSM
#define BUSWARE_CCD
#define RPI_TTY_FIX
+
+//#define CUL_HW_REVISION "CCD"
+
#endif
--- Devices/CCD/CCD.c Sun Oct 06 21:08:48 2013
+++ Devices/CCD/CCD.c Sun Jun 08 20:02:11 2014
@@ -35,7 +35,7 @@
#include "i2cmaster.h"
#include "ds1339.h"
-#ifdef HAS_ASKSIN
+#if defined(HAS_ASKSIN) || defined(HAS_ASKSIN_PLL_HELPER) || defined(HAS_MS_TIMER0) || defined(HAS_MS_TIMER3)
#include "rf_asksin.h"
#endif
@@ -132,7 +132,11 @@
// IR uses highspeed TIMER0 for sampling
OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
#else
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
+#else
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
@@ -141,6 +145,16 @@
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+#ifdef HAS_MS_TIMER3
+ uint8_t sreg = SREG;
+ cli();
+ OCR3A = 999; // 999 -> Timer3: 1ms = 8MHz/8/1000 interrupt clock
+ SREG = sreg;
+ TCCR3A = 0;
+ TCCR3B = _BV(CS31) | _BV(WGM32); // Timer3: 1us = 8MHz/8 base clock
+ TIMSK3 = _BV(OCIE3A);
+#endif
+
MCUSR &= ~(1 << WDRF); // Enable the watchdog
wdt_enable(WDTO_2S);
@@ -185,6 +199,9 @@
#endif
#ifdef HAS_MORITZ
rf_moritz_task();
+#endif
+#ifdef HAS_ASKSIN_PLL_HELPER
+ rf_asksin_check_PLL_task();
#endif
}
--- Devices/COC/board.h Mon Mar 17 14:45:54 2014
+++ Devices/COC/board.h Sun Jun 08 16:30:54 2014
@@ -45,13 +45,17 @@
#define HAS_RF_ROUTER // PROGMEM: 1248b RAM: 44b
#define FHTBUF_SIZE 174 // RAM: 174b
+//#define FHTBUF_SIZE 168 // RAM: 174b -6
#define RCV_BUCKETS 4 // RAM: 25b * bucket
#define RFR_DEBUG // PROGMEM: 354b RAM: 14b
#define FULL_CC1100_PA // PROGMEM: 108b
#define HAS_RAWSEND //
#define HAS_FASTRF // PROGMEM: 468b RAM: 1b
+#define HAS_ASKSIN_PLL_HELPER // noansi: check for PLL Lock and try recalibration, if not
#define HAS_ASKSIN
#define HAS_ASKSIN_FUP
+//#define HAS_MS_TIMER3 // RAM: +5b Timer3 for ms timestamp counter in asksin.c
+#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms increment
#define HAS_MORITZ
#define HAS_ESA
#define HAS_TX3
--- Devices/COC/COC.c Fri Mar 14 19:57:58 2014
+++ Devices/COC/COC.c Sun Jun 08 16:52:06 2014
@@ -35,7 +35,7 @@
#include "i2cmaster.h"
#include "ds1339.h"
-#ifdef HAS_ASKSIN
+#if defined(HAS_ASKSIN) || defined(HAS_ASKSIN_PLL_HELPER) || defined(HAS_MS_TIMER0) || defined(HAS_MS_TIMER3)
#include "rf_asksin.h"
#endif
@@ -133,7 +133,11 @@
// IR uses highspeed TIMER0 for sampling
OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
#else
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
+#else
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
@@ -142,6 +146,16 @@
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+#ifdef HAS_MS_TIMER3
+ uint8_t sreg = SREG;
+ cli();
+ OCR3A = 999; // 999 -> Timer3: 1ms = 8MHz/8/1000 interrupt clock
+ SREG = sreg;
+ TCCR3A = 0;
+ TCCR3B = _BV(CS31) | _BV(WGM32); // Timer3: 1us = 8MHz/8 base clock
+ TIMSK3 = _BV(OCIE3A);
+#endif
+
MCUSR &= ~(1 << WDRF); // Enable the watchdog
wdt_enable(WDTO_2S);
@@ -186,6 +200,9 @@
#endif
#ifdef HAS_MORITZ
rf_moritz_task();
+#endif
+#ifdef HAS_ASKSIN_PLL_HELPER
+ rf_asksin_check_PLL_task();
#endif
}
--- Devices/COC/makefile Tue Jun 25 08:38:20 2013
+++ Devices/COC/makefile Sat Jun 07 15:52:46 2014
@@ -100,7 +100,7 @@
all:
make TARGET=COC COCVERS=FULL mostly_clean build size
- make TARGET=COC.radio_only COCVERS=RADIO_ONLY mostly_clean build size
+ make TARGET=COC_radio_only COCVERS=RADIO_ONLY mostly_clean build size
build: elf hex eep lss sym
@@ -125,7 +125,7 @@
program_full: COCVERS=FULL
program_full: do_program
-program_radio_only: TARGET=COC.radio_only
+program_radio_only: TARGET=COC_radio_only
program_radio_only: COCVERS=RADIO_ONLY
program_radio_only: do_program
--- Devices/CSM/board.h Fri Mar 14 19:57:58 2014
+++ Devices/CSM/board.h Sun Jun 08 20:11:17 2014
@@ -64,6 +64,9 @@
#define HAS_RF_ROUTER // PROGMEM: 920b RAM: 38b
#define HAS_ASKSIN
#define HAS_ASKSIN_FUP
+//#define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#define HAS_MORITZ
#define HAS_ESA
#define HAS_INTERTECHNO
@@ -142,6 +145,26 @@
#define BOARD_ID_STR "CSM868"
#define BOARD_ID_STR433 "CSM433"
+
+#ifdef CSMV2
+//#define CUL_HW_REVISION "CSM_V2"
+#endif
+
+#ifdef CSMV3
+//#define CUL_HW_REVISION "CSM_V3"
+#endif
+
+#ifdef CSMV4
+//#define CUL_HW_REVISION "CSM_V4"
+#endif
+
+#ifdef TUXRAIL
+//#define CUL_HW_REVISION "TUXRAIL"
+#endif
+
+#ifdef TUXRADIO
+//#define CUL_HW_REVISION "TUXRADIO"
+#endif
#define HAS_UART 1
#define UART_BAUD_RATE 38400
--- Devices/CSM/CSM.c Fri Mar 14 19:57:58 2014
+++ Devices/CSM/CSM.c Sun Jun 08 20:13:52 2014
@@ -36,7 +36,7 @@
#include "intertechno.h"
#endif
-#ifdef HAS_ASKSIN
+#if defined(HAS_ASKSIN) || defined(HAS_ASKSIN_PLL_HELPER) || defined(HAS_MS_TIMER0) || defined(HAS_MS_TIMER3)
#include "rf_asksin.h"
#endif
@@ -149,7 +149,11 @@
// IR uses highspeed TIMER0 for sampling
OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
#else
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
+#else
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
@@ -158,6 +162,16 @@
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+#ifdef HAS_MS_TIMER3
+ uint8_t sreg = SREG;
+ cli();
+ OCR3A = 999; // 999 -> Timer3: 1ms = 8MHz/8/1000 interrupt clock
+ SREG = sreg;
+ TCCR3A = 0;
+ TCCR3B = _BV(CS31) | _BV(WGM32); // Timer3: 1us = 8MHz/8 base clock
+ TIMSK3 = _BV(OCIE3A);
+#endif
+
clock_prescale_set(clock_div_1);
MCUSR &= ~(1 << WDRF); // Enable the watchdog
@@ -206,6 +220,9 @@
#endif
#ifdef HAS_IRRX
ir_task();
+#endif
+#ifdef HAS_ASKSIN_PLL_HELPER
+ rf_asksin_check_PLL_task();
#endif
}
--- Devices/CUL/board.h Fri Apr 18 20:06:04 2014
+++ Devices/CUL/board.h Mon Jun 09 15:46:40 2014
@@ -15,16 +15,18 @@
#define HAS_FHT_80b // PROGMEM: 1374b, RAM: 90b
#define HAS_FHT_8v // PROGMEM: 586b RAM: 23b
#define HAS_RF_ROUTER // PROGMEM: 1248b RAM: 44b
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#if defined(CUL_V3) || defined(CUL_V4)
# define FHTBUF_SIZE 174 // RAM: 174b
+//# define FHTBUF_SIZE 168 // RAM: 174b -6
# define RCV_BUCKETS 4 // RAM: 25b * bucket
# define RFR_DEBUG // PROGMEM: 354b RAM: 14b
# define FULL_CC1100_PA // PROGMEM: 108b
# define HAS_RAWSEND //
# define HAS_FASTRF // PROGMEM: 468b RAM: 1b
-# define HAS_ASKSIN
-# define HAS_ASKSIN_FUP
+# define HAS_ASKSIN // RAM: 1b +1b
+# define HAS_ASKSIN_FUP // RAM: 1b
# define HAS_MORITZ
# define HAS_RWE
# define HAS_ESA
@@ -36,11 +38,15 @@
#endif
#if defined(CUL_V4)
+# define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms increment
# define TTY_BUFSIZE 64 // RAM: TTY_BUFSIZE*4
#endif
#if defined(CUL_V3)
+//# define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+# define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms increment
# define TTY_BUFSIZE 128 // RAM: TTY_BUFSIZE*4
+//# define TTY_BUFSIZE 152 // RAM: TTY_BUFSIZE*4
#endif
@@ -53,12 +59,15 @@
# define HAS_TX3
# define HAS_HOERMANN
# undef HAS_FHT_8v
+# undef HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not. Not enough free Flash
#endif
#ifdef CUL_V2_HM
# define CUL_V2
# define HAS_ASKSIN
+# define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms resolution
# define TTY_BUFSIZE 64
+//# define TTY_BUFSIZE 62 // RAM: -8b
# define RCV_BUCKETS 2
# undef HAS_RF_ROUTER
# undef HAS_FHT_80b
@@ -90,6 +99,7 @@
// No features to define below
#include <avr/io.h>
+
#include <avr/power.h>
#if !defined(clock_prescale_set) && __AVR_LIBC_VERSION__ < 10701UL
--- Devices/CUL/CUL.c Sat Mar 29 07:17:22 2014
+++ Devices/CUL/CUL.c Sun Jun 08 16:51:26 2014
@@ -3,11 +3,16 @@
Inpired by the MyUSB USBtoSerial demo, Copyright (C) Dean Camera, 2008.
*/
+#include <avr/io.h>
+
#include <avr/boot.h>
#include <avr/power.h>
#include <avr/eeprom.h>
#include <avr/interrupt.h>
-#include <avr/io.h>
+
+//#include <avr/io.h>
+
+
#include <avr/pgmspace.h>
#include <avr/wdt.h>
@@ -34,7 +39,7 @@
#ifdef HAS_MEMFN
#include "memory.h" // getfreemem
#endif
-#ifdef HAS_ASKSIN
+#if defined(HAS_ASKSIN) || defined(HAS_ASKSIN_PLL_HELPER) || defined(HAS_MS_TIMER0) || defined(HAS_MS_TIMER3)
#include "rf_asksin.h"
#endif
#ifdef HAS_MORITZ
@@ -132,13 +137,33 @@
// Setup the timers. Are needed for watchdog-reset
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250
+#ifdef HAS_IRRX
+ ir_init();
+ // IR uses highspeed TIMER0 for sampling
+ OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
+#else
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
+#else
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
+#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
TCCR1A = 0;
- TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+ TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+
+#ifdef HAS_MS_TIMER3
+ uint8_t sreg = SREG;
+ cli();
+ OCR3A = 999; // 999 -> Timer3: 1ms = 8MHz/8/1000 interrupt clock
+ SREG = sreg;
+ TCCR3A = 0;
+ TCCR3B = _BV(CS31) | _BV(WGM32); // Timer3: 1us = 8MHz/8 base clock
+ TIMSK3 = _BV(OCIE3A);
+#endif
MCUSR &= ~(1 << WDRF); // Enable the watchdog
@@ -178,5 +203,9 @@
#ifdef HAS_RWE
rf_rwe_task();
#endif
+#ifdef HAS_ASKSIN_PLL_HELPER
+ rf_asksin_check_PLL_task();
+#endif
+
}
}
--- Devices/CUN/board.h Wed Jul 11 15:19:20 2012
+++ Devices/CUN/board.h Sat Jun 07 17:21:32 2014
@@ -102,6 +102,8 @@
#define HAS_RAWSEND // PROGMEM: 198b RAM: 4b
#define HAS_FASTRF // PROGMEM: 362+106 RAM: 1b
#define HAS_ASKSIN
+//#define HAS_MS_TIMER0 // noansi: Timer0 for ms timestamp counter in asksin.c, 4ms resolution
+//#define HAS_MS_TIMER3 // noansi: Timer3 for ms timestamp counter in asksin.c, only if supported by CPU
#define HAS_ESA
#define HAS_TX3
#define HAS_INTERTECHNO
--- Devices/CUN/CUN.c Tue Nov 27 22:12:52 2012
+++ Devices/CUN/CUN.c Sat Jun 07 18:06:15 2014
@@ -153,13 +153,33 @@
while(tx_report); // reboot if the bss is not initialized
// Setup the timers. Are needed for watchdog-reset
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250
+#ifdef HAS_IRRX
+ ir_init();
+ // IR uses highspeed TIMER0 for sampling
+ OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
+#else
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
+#else
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
+#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+
+#ifdef HAS_MS_TIMER3
+ uint8_t sreg = SREG;
+ cli();
+ OCR3A = 999; // 999 -> Timer3: 1ms = 8MHz/8/1000 interrupt clock
+ SREG = sreg;
+ TCCR3A = 0;
+ TCCR3B = _BV(CS31) | _BV(WGM32); // Timer3: 1us = 8MHz/8 base clock
+ TIMSK3 = _BV(OCIE3A);
+#endif
MCUSR &= ~(1 << WDRF); // Enable the watchdog
--- Devices/CUNO/board.h Fri Mar 14 19:57:58 2014
+++ Devices/CUNO/board.h Sun Jun 08 20:20:07 2014
@@ -69,6 +69,9 @@
#define HAS_FASTRF // PROGMEM: 468b RAM: 1b
#define HAS_ASKSIN
#define HAS_ASKSIN_FUP
+//#define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#define HAS_ESA
#define HAS_TX3
#define HAS_INTERTECHNO
@@ -80,6 +83,7 @@
#define BOARD_ID_STR "CUNO868"
#define BOARD_ID_STR433 "CUNO433"
+//#define CUL_HW_REVISION "CUNO"
#define HAS_UART 1
#define UART_BAUD_RATE 38400
--- Devices/CUNO/CUNO.c Tue Nov 27 22:12:52 2012
+++ Devices/CUNO/CUNO.c Sun Jun 08 20:21:50 2014
@@ -37,7 +37,7 @@
#include "i2cmaster.h"
-#ifdef HAS_ASKSIN
+#if defined(HAS_ASKSIN) || defined(HAS_ASKSIN_PLL_HELPER) || defined(HAS_MS_TIMER0) || defined(HAS_MS_TIMER3)
#include "rf_asksin.h"
#endif
@@ -147,7 +147,17 @@
// Setup the timers. Are needed for watchdog-reset
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
+#ifdef HAS_IRRX
+ ir_init();
+ // IR uses highspeed TIMER0 for sampling
+ OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
+#else
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
+#else
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
+#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
@@ -155,6 +165,16 @@
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+#ifdef HAS_MS_TIMER3
+ uint8_t sreg = SREG;
+ cli();
+ OCR3A = 999; // 999 -> Timer3: 1ms = 8MHz/8/1000 interrupt clock
+ SREG = sreg;
+ TCCR3A = 0;
+ TCCR3B = _BV(CS31) | _BV(WGM32); // Timer3: 1us = 8MHz/8 base clock
+ TIMSK3 = _BV(OCIE3A);
+#endif
+
clock_prescale_set(clock_div_1);
MCUSR &= ~(1 << WDRF); // Enable the watchdog
@@ -196,6 +216,9 @@
#endif
#ifdef HAS_ETHERNET
Ethernet_Task();
+#endif
+#ifdef HAS_ASKSIN_PLL_HELPER
+ rf_asksin_check_PLL_task();
#endif
}
--- Devices/CUNO2/board.h Fri Mar 14 19:57:58 2014
+++ Devices/CUNO2/board.h Sun Jun 08 20:25:49 2014
@@ -66,6 +66,9 @@
#define HAS_FASTRF // PROGMEM: 468b RAM: 1b
#define HAS_ASKSIN
#define HAS_ASKSIN_FUP
+//#define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#define HAS_ESA
#define HAS_TX3
#define HAS_INTERTECHNO
@@ -138,6 +141,8 @@
#define TTY_BUFSIZE 1024
#define BUSWARE_CUNO2
+
+//#define CUL_HW_REVISION "CUNO2"
#ifndef eeprom_update_byte
#define eeprom_update_byte eeprom_write_byte
--- Devices/CUNO2/CUNO2.c Sun Nov 03 00:01:38 2013
+++ Devices/CUNO2/CUNO2.c Sun Jun 08 20:23:40 2014
@@ -52,7 +52,7 @@
#include "i2cmaster.h"
-#ifdef HAS_ASKSIN
+#if defined(HAS_ASKSIN) || defined(HAS_ASKSIN_PLL_HELPER) || defined(HAS_MS_TIMER0) || defined(HAS_MS_TIMER3)
#include "rf_asksin.h"
#endif
@@ -156,12 +156,16 @@
// Setup the timers. Are needed for watchdog-reset
-#if defined (HAS_IRRX) || defined (HAS_IRTX)
+#ifdef HAS_IRRX
ir_init();
// IR uses highspeed TIMER0 for sampling
- OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz Fac: 125
+ OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
+#else
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
#else
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
#endif
TCCR0B = _BV(CS02);
@@ -171,6 +175,16 @@
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+#ifdef HAS_MS_TIMER3
+ uint8_t sreg = SREG;
+ cli();
+ OCR3A = 999; // 999 -> Timer3: 1ms = 8MHz/8/1000 interrupt clock
+ SREG = sreg;
+ TCCR3A = 0;
+ TCCR3B = _BV(CS31) | _BV(WGM32); // Timer3: 1us = 8MHz/8 base clock
+ TIMSK3 = _BV(OCIE3A);
+#endif
+
clock_prescale_set(clock_div_1);
MCUSR &= ~(1 << WDRF); // Enable the watchdog
@@ -249,6 +263,9 @@
#ifdef HAS_HELIOS
helios_task();
#endif
+#ifdef HAS_ASKSIN_PLL_HELPER
+ rf_asksin_check_PLL_task();
+#endif
}
}
--- Devices/CUR/board.h Wed Jul 11 15:19:20 2012
+++ Devices/CUR/board.h Sun Jun 08 20:46:24 2014
@@ -25,15 +25,19 @@
#define FULL_CC1100_PA // PROGMEM: 100b
#define HAS_FASTRF // PROGMEM: 362b RAM: 1b
#define HAS_RAWSEND // PROGMEM: 90b RAM: 6b
-#define HAS_ASKSIN
+//#define HAS_ASKSIN // why is it here?
+//#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#define HAS_ESA
#define HAS_TX3
#define HAS_HOERMANN
#ifdef CURV3
# include "board_v3.h"
+//#define CUL_HW_REVISION "CUR_V3"
#else
# include "board_v2.h"
+//#define CUL_HW_REVISION "CUR_V2"
#endif
#endif
--- Devices/CUR/CUR.c Tue Nov 27 22:12:52 2012
+++ Devices/CUR/CUR.c Sun Jun 08 20:37:01 2014
@@ -40,6 +40,10 @@
#include "fastrf.h"
#include "rf_router.h"
+#if defined(HAS_ASKSIN) || defined(HAS_ASKSIN_PLL_HELPER) || defined(HAS_MS_TIMER0) || defined(HAS_MS_TIMER3)
+#include "rf_asksin.h"
+#endif
+
df_chip_t df;
const PROGMEM t_fntab fntab[] = {
@@ -106,7 +110,17 @@
}
// Setup the timers. Are needed for watchdog-reset
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250
+#ifdef HAS_IRRX
+ ir_init();
+ // IR uses highspeed TIMER0 for sampling
+ OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
+#else
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
+#else
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
+#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
@@ -150,5 +164,8 @@
FastRF_Task();
rf_router_task();
JOY_Task();
+#ifdef HAS_ASKSIN_PLL_HELPER
+ rf_asksin_check_PLL_task();
+#endif
}
}
--- Devices/CUR/makefile Sun Nov 13 21:23:08 2011
+++ Devices/CUR/makefile Sun Jun 08 20:42:00 2014
@@ -22,6 +22,7 @@
../../clib/rf_send.c \
../../clib/rf_receive.c \
../../clib/fht.c \
+ ../../clib/rf_asksin.c \
../../clib/ttydata.c \
../../clib/pcf8833.c \
../../clib/menu.c \
--- Devices/CUR/makefile.myusb Sun Nov 01 08:37:40 2009
+++ Devices/CUR/makefile.myusb Sun Jun 08 20:42:47 2014
@@ -22,6 +22,7 @@
../../clib/rf_send.c \
../../clib/rf_receive.c \
../../clib/fht.c \
+ ../../clib/rf_asksin.c \
../../clib/ttydata.c \
../../clib/pcf8833.c \
../../clib/menu.c \
--- Devices/RFbee/board.h Thu Mar 13 23:05:46 2014
+++ Devices/RFbee/board.h Sun Jun 08 20:50:21 2014
@@ -11,6 +11,9 @@
#define HAS_FASTRF // PROGMEM: 468b RAM: 1b
#define HAS_ASKSIN
#define HAS_ASKSIN_FUP
+//#define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#undef HAS_ESA
#define HAS_INTERTECHNO
#define HAS_MORITZ
@@ -53,6 +56,7 @@
#define LED_PIN 6
#define BOARD_ID_STR "RFbee"
+//#define CUL_HW_REVISION "RFbee"
#define HAS_UART 1
#define UART_BAUD_RATE 38400
--- Devices/RFbee/RFbee.c Thu Mar 13 23:05:46 2014
+++ Devices/RFbee/RFbee.c Sun Jun 08 20:48:41 2014
@@ -40,7 +40,7 @@
#include "intertechno.h"
#endif
-#ifdef HAS_ASKSIN
+#if defined(HAS_ASKSIN) || defined(HAS_ASKSIN_PLL_HELPER) || defined(HAS_MS_TIMER0) || defined(HAS_MS_TIMER3)
#include "rf_asksin.h"
#endif
@@ -107,7 +107,17 @@
eeprom_init();
// Setup the timers. Are needed for watchdog-reset
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
+#ifdef HAS_IRRX
+ ir_init();
+ // IR uses highspeed TIMER0 for sampling
+ OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
+#else
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
+#else
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
+#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
@@ -115,6 +125,16 @@
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+#ifdef HAS_MS_TIMER3
+ uint8_t sreg = SREG;
+ cli();
+ OCR3A = 999; // 999 -> Timer3: 1ms = 8MHz/8/1000 interrupt clock
+ SREG = sreg;
+ TCCR3A = 0;
+ TCCR3B = _BV(CS31) | _BV(WGM32); // Timer3: 1us = 8MHz/8 base clock
+ TIMSK3 = _BV(OCIE3A);
+#endif
+
clock_prescale_set(clock_div_1);
MCUSR &= ~(1 << WDRF); // Enable the watchdog
@@ -153,6 +173,9 @@
#endif
#ifdef HAS_RWE
rf_rwe_task();
+#endif
+#ifdef HAS_ASKSIN_PLL_HELPER
+ rf_asksin_check_PLL_task();
#endif
}
}
--- Devices/SCC/board.h Mon Mar 17 14:50:20 2014
+++ Devices/SCC/board.h Sun Jun 08 20:52:46 2014
@@ -49,6 +49,9 @@
#define HAS_FASTRF // PROGMEM: 468b RAM: 1b
#define HAS_RF_ROUTER // PROGMEM: 920b RAM: 38b
#define HAS_ASKSIN
+//#define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#define HAS_MORITZ
#define HAS_ESA
#define HAS_INTERTECHNO
@@ -77,5 +80,7 @@
#define BUSWARE_CSM
#define BUSWARE_SCC
#define RPI_TTY_FIX
+
+//#define CUL_HW_REVISION "SCC"
#endif
--- Devices/SCC/SCC.c Mon Mar 17 14:50:20 2014
+++ Devices/SCC/SCC.c Sun Jun 08 20:54:05 2014
@@ -36,7 +36,7 @@
#include "intertechno.h"
#endif
-#ifdef HAS_ASKSIN
+#if defined(HAS_ASKSIN) || defined(HAS_ASKSIN_PLL_HELPER) || defined(HAS_MS_TIMER0) || defined(HAS_MS_TIMER3)
#include "rf_asksin.h"
#endif
@@ -132,7 +132,17 @@
// }
// Setup the timers. Are needed for watchdog-reset
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
+#ifdef HAS_IRRX
+ ir_init();
+ // IR uses highspeed TIMER0 for sampling
+ OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
+#else
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
+#else
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
+#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
@@ -140,6 +150,16 @@
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+#ifdef HAS_MS_TIMER3
+ uint8_t sreg = SREG;
+ cli();
+ OCR3A = 999; // 999 -> Timer3: 1ms = 8MHz/8/1000 interrupt clock
+ SREG = sreg;
+ TCCR3A = 0;
+ TCCR3B = _BV(CS31) | _BV(WGM32); // Timer3: 1us = 8MHz/8 base clock
+ TIMSK3 = _BV(OCIE3A);
+#endif
+
clock_prescale_set(clock_div_1);
MCUSR &= ~(1 << WDRF); // Enable the watchdog
@@ -189,6 +209,9 @@
#endif
#ifdef HAS_STACKING
stacking_task();
+#endif
+#ifdef HAS_ASKSIN_PLL_HELPER
+ rf_asksin_check_PLL_task();
#endif
}
--- Devices/TuxRadio/board.h Wed Jul 11 15:19:20 2012
+++ Devices/TuxRadio/board.h Sun Jun 08 20:59:48 2014
@@ -67,8 +67,12 @@
#define HAS_RAWSEND //
#define HAS_FASTRF // PROGMEM: 468b RAM: 1b
//#define HAS_ASKSIN
+//#define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+//#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
//#define HAS_ESA
#define BUSWARE_CSM
+//#define CUL_HW_REVISION "TuxRadio"
#endif
--- Devices/TuxRadio/CSM.c Tue Nov 27 22:12:52 2012
+++ Devices/TuxRadio/CSM.c Sun Jun 08 21:01:19 2014
@@ -32,7 +32,7 @@
#include "rf_router.h"
#include "memory.h"
-#ifdef HAS_ASKSIN
+#if defined(HAS_ASKSIN) || defined(HAS_ASKSIN_PLL_HELPER) || defined(HAS_MS_TIMER0) || defined(HAS_MS_TIMER3)
#include "rf_asksin.h"
#endif
@@ -108,7 +108,11 @@
// IR uses highspeed TIMER0 for sampling
OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
#else
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
+#else
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
@@ -117,6 +121,16 @@
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+#ifdef HAS_MS_TIMER3
+ uint8_t sreg = SREG;
+ cli();
+ OCR3A = 999; // 999 -> Timer3: 1ms = 8MHz/8/1000 interrupt clock
+ SREG = sreg;
+ TCCR3A = 0;
+ TCCR3B = _BV(CS31) | _BV(WGM32); // Timer3: 1us = 8MHz/8 base clock
+ TIMSK3 = _BV(OCIE3A);
+#endif
+
MCUSR &= ~(1 << WDRF); // Enable the watchdog
wdt_enable(WDTO_2S);
@@ -161,6 +175,9 @@
#endif
#ifdef HAS_IRRX
ir_task();
+#endif
+#ifdef HAS_ASKSIN_PLL_HELPER
+ rf_asksin_check_PLL_task();
#endif
}
--- Devices/TuxRadio2/board.h Fri Jan 11 14:08:54 2013
+++ Devices/TuxRadio2/board.h Sun Jun 08 21:04:11 2014
@@ -51,6 +51,9 @@
#define HAS_RAWSEND //
#define HAS_FASTRF // PROGMEM: 468b RAM: 1b
#define HAS_ASKSIN
+//#define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#define HAS_ESA
#define HAS_TX3
#define HAS_INTERTECHNO
@@ -59,6 +62,8 @@
#define HAS_MORITZ
#define BUSWARE_CSM
+
+//#define CUL_HW_REVISION "TuxRadio2"
#endif
--- Devices/TuxRadio2/CSM.c Sat Sep 21 18:10:34 2013
+++ Devices/TuxRadio2/CSM.c Sun Jun 08 21:02:41 2014
@@ -36,7 +36,7 @@
#include "rf_moritz.h"
#endif
-#ifdef HAS_ASKSIN
+#if defined(HAS_ASKSIN) || defined(HAS_ASKSIN_PLL_HELPER) || defined(HAS_MS_TIMER0) || defined(HAS_MS_TIMER3)
#include "rf_asksin.h"
#endif
@@ -112,7 +112,11 @@
// IR uses highspeed TIMER0 for sampling
OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
#else
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
+#else
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
@@ -121,6 +125,16 @@
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+#ifdef HAS_MS_TIMER3
+ uint8_t sreg = SREG;
+ cli();
+ OCR3A = 999; // 999 -> Timer3: 1ms = 8MHz/8/1000 interrupt clock
+ SREG = sreg;
+ TCCR3A = 0;
+ TCCR3B = _BV(CS31) | _BV(WGM32); // Timer3: 1us = 8MHz/8 base clock
+ TIMSK3 = _BV(OCIE3A);
+#endif
+
MCUSR &= ~(1 << WDRF); // Enable the watchdog
wdt_enable(WDTO_2S);
@@ -168,6 +182,9 @@
#endif
#ifdef HAS_MORITZ
rf_moritz_task();
+#endif
+#ifdef HAS_ASKSIN_PLL_HELPER
+ rf_asksin_check_PLL_task();
#endif
}
--- Devices/zCSM/board.h Fri Apr 12 16:03:32 2013
+++ Devices/zCSM/board.h Sun Jun 08 20:55:54 2014
@@ -51,6 +51,9 @@
#define HAS_RAWSEND //
#define HAS_FASTRF // PROGMEM: 468b RAM: 1b
#define HAS_ASKSIN
+//#define HAS_MS_TIMER3 // RAM: +5b noansi: Timer3 for ms timestamp counter in asksin.c
+#define HAS_MS_TIMER0 // RAM: +5b noansi: Timer0 for ms timestamp counter in asksin.c, 4ms (IR 8ms) increment
+#define HAS_ASKSIN_PLL_HELPER // RAM: +1b noansi: check for PLL Lock and try recalibration, if not
#define HAS_MORITZ
#define HAS_ESA
#define HAS_INTERTECHNO
@@ -64,5 +67,7 @@
#define TTY_BUFSIZE 128
#define BUSWARE_CSM
+
+//#define CUL_HW_REVISION "zCSM"
#endif
--- Devices/zCSM/CSM.c Fri Apr 12 16:03:32 2013
+++ Devices/zCSM/CSM.c Sun Jun 08 20:56:56 2014
@@ -40,7 +40,7 @@
#include "intertechno.h"
#endif
-#ifdef HAS_ASKSIN
+#if defined(HAS_ASKSIN) || defined(HAS_ASKSIN_PLL_HELPER) || defined(HAS_MS_TIMER0) || defined(HAS_MS_TIMER3)
#include "rf_asksin.h"
#endif
@@ -148,7 +148,11 @@
// IR uses highspeed TIMER0 for sampling
OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
#else
- OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
+#if defined(HAS_MS_TIMER0) && !defined(HAS_MS_TIMER3)
+ OCR0A = 124; // Timer0: 0.004s = 8MHz/256/125 interrupt clock
+#else
+ OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 interrupt clock
+#endif
#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
@@ -157,6 +161,16 @@
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
+#ifdef HAS_MS_TIMER3
+ uint8_t sreg = SREG;
+ cli();
+ OCR3A = 999; // 999 -> Timer3: 1ms = 8MHz/8/1000 interrupt clock
+ SREG = sreg;
+ TCCR3A = 0;
+ TCCR3B = _BV(CS31) | _BV(WGM32); // Timer3: 1us = 8MHz/8 base clock
+ TIMSK3 = _BV(OCIE3A);
+#endif
+
clock_prescale_set(clock_div_1);
MCUSR &= ~(1 << WDRF); // Enable the watchdog
@@ -205,6 +219,9 @@
#endif
#ifdef HAS_MORITZ
rf_moritz_task();
+#endif
+#ifdef HAS_ASKSIN_PLL_HELPER
+ rf_asksin_check_PLL_task();
#endif
}